The present invention relates to transistor design, and more particularly, to a novel field-effect transistor (FET) design.
FETs are a type of transistor that have source, drain, and gate terminals. Typically, integrated circuits include many FETs on a single substrate. As circuits become miniaturized, the size of FETs become smaller and smaller. Smaller FETs tend to have higher parasitic contact resistance due to a smaller contact area in the source-drain region. The parasitic contact resistance can dominate circuit delay during the circuit's operation.